Semiconductor device including chips with electrically-isolated test elements and its manufacturing method

ABSTRACT

In a semiconductor device including a semiconductor substrate and an electrode pad formed over the semiconductor substrate, at least one of test element is formed in a region of the semiconductor substrate beneath the electrode pad. The test element is electrically isolated from upper conductive layers outside of the region and the electrode pad.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device including testelement group (TEG) elements and its manufacturing method.

2. Description of the Related Art

Generally, in a method for manufacturing a semiconductor device (wafer),TEG elements are formed in the semiconductor device, so that theelectrical properties thereof can be evaluated by contacting probes tothe TEG elements.

In a first prior art semiconductor device (wafer) (see:JP-2002-313864-A), a semiconductor wafer is divided into product chipareas. Also, TEG elements are formed beneath electrode pads in each ofthe product chip areas, while test electrode pads are formed in scribeline areas. The TEG elements are electrically connected to the testelectrode pads. Therefore, the electrical properties of thesemiconductor wafer can be evaluated by contacting probes to the testelectrode pads.

In the above-described first prior art semiconductor device (wafer),since the TEG elements are covered by the electrode pads in the productchip areas, a third party including users cannot observe the TEGelements. In addition, after the semiconductor wafer is diced andassembled into chip packages, the test electrode pads in the scribe lineareas are scrapped. Therefore, the electrical properties of thesemiconductor wafer are never evaluated by a third party includingusers. Also, since the TEG elements and the test electrode pads do notrequire additional occupied areas, the integration of the product chipsis not affected. Further, since the TEG elements and the test electrodepads are formed simultaneously by the manufacturing steps for the otherportions of the product chip areas, the manufacturing cost hardlyincreases. Still further, since test chip areas for only TEG elementsare not included in the semiconductor wafer, the manufacturing steps arenot so complex, which also would not increase the manufacturing cost.

In the above-described first semiconductor wafer, however, after thesemiconductor wafer is diced and assembled into chip packages, it isimpossible for the manufacturer per se to evaluate the electricalproperties of the semiconductor wafer. Note that, even after thesemiconductor wafer is diced and assembled into the chip packages, theelectrical properties of the chip packages are often required to beevaluated under various environments such as temperature environment andhumidity environment.

In a second prior art semiconductor device (wafer) (see: JP-9-321104-A),a semiconductor wafer is also divided into product chip areas. Also, TEGelements are formed beneath main electrode pads in each of the productchip areas, and sub electrode pads (test electrode pads) are formed ineach of the product chip areas. The TEG elements are electricallyconnected to the test electrode pads as well as the main electrode pads.Therefore, the electrical properties of the semiconductor wafer can beevaluated by contacting probes to the test electrode pads.

In the above-described second prior art semiconductor wafer, even afterthe semiconductor wafer is diced and assembled into chip packages, sincethe test electrode pads are not scrapped, the manufacturer per se canevaluate the electrical properties of the semiconductor wafer. Also,since the TEG elements and the test electrode pads are formedsimultaneously by the manufacturing steps for the other portions of theproduct chips, the manufacturing cost hardly increases. Further, sincetest chip areas for only TEG elements are not provided in thesemiconductor wafer, the manufacturing steps are not so complex, whichalso would not increase the manufacturing cost.

In the above-described second prior art semiconductor wafer, however,although the TEG elements are covered by the main electrode pads, evenwhen the semiconductor wafer is diced and assembled into chip packages,the test electrode pads are not scrapped. Therefore, a third partyincluding users can easily evaluate the electrical properties of thesemiconductor wafer. Also, since the sub electrode pads (test electrodepads) are required in each of the product chip areas, the integrationwould be negatively affected. Further, bonding wire of the mainelectrode pads would be short-circuited to the sub electrode pads (testelectrode pads).

In a third prior art semiconductor device (wafer), a semiconductor waferis divided into product chip areas where TEG elements are not formed andtest chip areas where various kinds of TEG elements and their testelectrode pads are formed.

In the above-described third prior art semiconductor wafer, even afterthe semiconductor wafer is diced and assembled into chip packages, sincetest chip packages are obtained, the manufacturer per se can evaluatethe electrical properties of the semiconductor wafer. Also, since theTEG elements are not included in the product chip areas, the electricalproperties of the semiconductor wafer are never evaluated by a thirdparty including users. Further, since the product chip areas do notrequire additional occupied areas, the integration of the product chipsis not affected.

In the above-described third prior art semiconductor wafer, however,since the manufacturing steps for the product chip areas are differentfrom those for the test chip areas, the manufacturing steps becomecomplex, which would increase the manufacturing cost. Particularly, theresult of the test chip areas by chemical mechanical polishing (CMP)steps and etching steps affects the product chip areas. As a result, theproperties of the product chips would deteriorate.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a highly-integrated,inexpensive and non-complex semiconductor device where the manufacturerper se can evaluate the electrical properties of product chips while athird party including users cannot evaluate them even after thesemiconductor device is diced and assembled into the semiconductorchips.

Another object is to provide a method for manufacturing such asemiconductor device.

According to the present invention, in a semiconductor device includinga semiconductor substrate and an electrode pad-formed over thesemiconductor substrate, at least one of test element is formed in aregion of the semiconductor substrate beneath the electrode pad. Thetest element is electrically isolated from upper conductive layersoutside of the region and the electrode pad. As a result, when thesemiconductor device is diced and assembled into semiconductor chips,the manufacturer per se can evaluate the semiconductor device, while athird party including users cannot evaluate the semiconductor device dueto the electrical disconnection between the test element and theelectrode pad. In this case, since the test element is covered by theelectrode pad, a third party cannot find the test element. Also, sincethe test element does not require additional occupied areas, theintegration is not affected. Further, since the test element can beformed by the manufacturing steps for the other portions, themanufacturing cost hardly increases. Still further, since the structurecan be the same as that of the test chips except for the electricalconnection/disconnection between the test element and the electrodepads, the manufacturing steps would not be complex, which would notincrease the manufacturing cost and also the properties would notdeteriorate.

Also, at least one circuit element is formed in the above-mentionedregion. In this case, the circuit element is electrically connected toone of the upper conductive layers and the electrode pad.

Further, in a method for manufacturing a semiconductor device dividedinto product chip areas, at least one circuit element and at least onetest element are formed in each of the product chip areas. Then, aconnection structure is formed in each of the product chip areas. Then,electrode pads are formed in each of the product chip areas. Finally,the product chip areas are diced and assembled into chip packages. Inthis case, the circuit element is electrically connected through theconnection structure to some of the electrode pads, while the testelement is formed beneath one of the electrode pads and electricallyisolated from the electrode pads without being connected to theconnection structure.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from thedescription set forth below, with reference to the accompanyingdrawings, wherein:

FIG. 1 is a plan view illustrating a first embodiment of thesemiconductor wafer according to the present invention;

FIG. 2 is a partial enlargement as indicated by X in FIG. 1;

FIG. 3 is a cross-sectional view taken along the line Y-Y in FIG. 2;

FIGS. 4A, 4B and 4C are cross-sectional views for explaining a methodfor manufacturing the semiconductor wafer of FIG. 1;

FIG. 5 is a cross-sectional view of FIG. 3 where no test element isprovided in the product chip area;

FIG. 6 is a plan view illustrating a second embodiment of thesemiconductor wafer according to the present invention;

FIG. 7 is a plan view illustrating a third embodiment of thesemiconductor wafer according to the present invention.

FIG. 8 is a cross-sectional view illustrating a modification of FIG. 3;

FIGS. 9, 10, 11, 12 and 13 are plan views illustrating modifications ofFIG. 2;

FIGS. 14A and 14B are cross-sectional views of modifications of the testelements of FIG. 3 where resistance elements are provided as such testelements; and

FIGS. 15A and 15B are cross-sectional views of modifications of the testelements of FIG. 3 where capacitance elements are provided as such testelements.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In FIG. 1, which illustrates a first embodiment of the semiconductordevice (wafer) according to the present invention, a semiconductor waferis divided into a plurality of product chips PC and a plurality of testchips TC. In this case, the number of the product chips PC is muchlarger than that of the test chips TC.

In FIG. 2, which is a partial enlargement as indicated by X in FIG. 1,the product chip PC and the test chip TC are separated by a scribe linearea SL. Electrode pads P₁, P₂, P₃ and P₄ are provided on the peripheryof the product chip PC, and electrode pads P₅, P₆, P₇ and P₈ areprovided on the periphery of the test chip TC.

Also, in the product chip PC, a TEG element T₁ is formed completelybeneath one of the electrode pads such as P₃. Similarly, in the testchip TC, a TEG element T₂ is formed completely beneath one of theelectrode pads such as P₆. Note that the arrangement of the TEG elementsin the product chips PC is the same as that in the test chips TC, sothat the manufacturing steps therefor can be simplified.

In the product chip PC, the TEG element T₁ is not electrically connectedto any of the electrode pads P₁, P₂, P₃ and P₄. In other words, the TEGelement T₁ is electrically isolated from the electrode pads P₁, P₂, P₃and P₄. Note that the electrode pads P₁, P₂, P₃ and P₄ are electricallyconnected via connection lines C₁, C₂, C₃ and C₄ to circuit elements(shown not in FIG. 2, but shown in FIG. 3).

On the other hand, in the test chip TC, the TEG element T₂ iselectrically connected to some of the electrode pads P₅, P₆, P₇ and P₈.For example, note that the electrode pads P₅, P₇ and P₈ are electricallyconnected via connection lines C₅, C₇ and C₈ to circuit elements (shownnot in FIG. 2, but shown in FIG. 3).

In FIG. 3, which is a cross-sectional view taken along the line Y-Y′ inFIG. 2, reference numeral 1 designates a p⁻-type monocrystalline siliconsubstrate on which gate electrodes 2 made of polycrystalline silicon orthe like are formed via a gate insulating layer (not shown). Also,n⁺-type impurity diffusion regions 3 are formed in self-alignment withthe gate electrodes 2. As a result, in the product chip PC, a circuitelement CE₁ is formed by one MOS transistor and a TEG element T₁ isformed by one MOS transistor. Similarly, a TEG element T₂ is formed byone MOS transistor and a circuit element CE₂ is formed by one MOStransistor.

Also, an insulating layer 4 is formed where contact structures 4 a areformed and reach the impurity regions 3. Connection layers 4 b areformed on the contact structures 4 a.

Further, an insulating layer 5 is formed where through structures 5 aare formed and reach the gate electrodes 2 and the connection layers 4b. Connection layers 5 b are formed on the through structures 5 a.

Additionally, an insulating layer 6 is formed where through structures 6a are formed and reach the connection layers 5 b. Electrode pads P₁, P₂,. . . , P₈ are formed on the through structures 6 a and the insulatinglayer 6.

Finally, a passivation layer 7 is formed and perforated to expose theelectrode pads P₁, P₂, . . . , P₈, thus completing the semiconductorwafer of FIG. 1.

In FIG. 3, the electrode pad P₂ is connected via a connection line C₂formed by the through structure 6 a, the connection layer 5 b and thethrough structure 5 a to the gate electrode 2 of the circuit elementCE₁. The electrode pad P₃ is connected via a connection line C₃ (notshown) to a circuit element (not shown). The electrode pad P₄ isconnected via a connection line C₄ (not shown) to a circuit element (notshown). The electrode pad P₅ is connected via a connection line C₅formed by the through structure 6 a, the connection layer 5 b, thethrough structure 5 a, the connection layer 4 b and the contactstructure 4 a to the impurity region 3 of the TEG element T₂. Theelectrode pad P₆ is not electrically connected to any element. Theelectrode pad P₇ is connected via a connection line C₇ formed by thethrough structure 6 a, the connection layer 5 b, the through structure 5a, the connection layer 4 b and the contact structure 4 a to theimpurity region 3 of the TEG element T₂. The electrode pad P₈ isconnected via a connection line C₈ formed by the through structure 6 a,the connection layer 5 b, the through structure 5 a, the connectionlayer 4 b and the contact structure 4 a to the gate electrode 2 of theTEG element T₂.

A method for manufacturing the semiconductor wafer of FIGS. 1, 2 and 3will be explained next in detail with reference to FIGS. 4A, 4B and 4Cas well as FIG. 3.

First, referring to FIG. 4A, a p⁻-type monocrystalline silicon substrate1 is thermally oxidized to form a gate insulating layer (not shown) madeof silicon dioxide. Then, gate electrode layer made of polycrystallinesilicon or the like is deposited on the gate insulating layer, and ispatterned by a photolithography and etching process to form gateelectrodes 2. Then, n-type impurities are implanted and diffused intothe silicon substrate 1 in self-alignment with the gate electrodes 2 toform n⁺-type impurity diffusion regions 3 which serve as source anddrain regions of MOS transistors. Then, an insulating layer is depositedon the entire surface, and contact holes are perforated therein. Then,contact structures 4 a are buried in the contact holes. Then, aconductive layer is deposited on the entire surface and is patterned bya photolithography and etching process to form connection layers 4 b onthe contact structures 4 a.

Next, referring to FIG. 4B, an insulating layer 5 is deposited on theentire surface, and throughholes are perforated therein. Then, throughstructures 5 a are buried in the throughholes. Then, a conductive layeris deposited on the entire surface, and is patterned by aphotolithography and etching process to form connection layers 5 b onthe through structures 5 a.

Next, referring to FIG. 4C, an insulating layer 6 is deposited on theentire surface, and throughholes are perforated therein. Then, throughstructures 6 a are buried in the throughholes. Then, a conductive layeris deposited on the entire surface and is patterned by aphotolithography and etching process to form electrode pads P₁, P₂, . .. , P₈ on the through structures 6 a.

Next, referring to FIG. 3, a passivation layer 7 is deposited on theentire surface, and is perforated to expose the electrode pads P₁, P₂, .. . , P₈.

Finally, the product chips PC and the test chips TC are diced andassembled into chip packages where wires are bonded between theelectrode pads P₁, P₂, . . . , P₈ and external leads of the packages.

In FIGS. 3, 4A, 4B and 4C, the contact structures 4 a and the connectionlayers 4 b are provided for the TEG element T₁ of the product chip PCand the TEG element T₂ of the test chip TC. On the other hand, thethrough structures 5 a, the connection layers 5 b and the throughstructures 6 a are not provided for the TEG element T₁ of the productchip PC, while the through structures 5 a, the connection layers 5 b andthe through structures 6 a are provided for the TEG element T₂ of thetest chip TC. As a result, the TEG element T₁ of the product chip PC⁺ iselectrically isolated from the electrode pads thereof. On the otherhand, the TEG element T₂ Of the test chip TC is electrically connectedto some of the electrode pads thereof. Also, the manufacturer per se canevaluate the semiconductor wafer by testing the TEG element T₂ of thetest chip TC, while a third party including users cannot evaluate thesemiconductor device (in this case, the product chip PC) due to theelectrical isolation of the TEG element T₁ and the electrode pads. Inthis case, since the test element T₁ is covered by the electrode pad,the third party cannot find the TEG element T₁ of the product chip PC.Also, since the TEG element T₁ is provided beneath the electrode pad P₃,which does not require additional occupied areas, the integration of theproduct chip PC is not affected. Further, since the TEG element T₁ canbe formed by the manufacturing steps for the other portions of theproduct chip PC except for the through structures 5 a, the connectionlayers 5 b and the through structures 6 a, the manufacturing cost hardlyincreases. Still further, since the structure of the product chips canbe the same as that of the test chips except for the electricalconnection/disconnection between the TEG element T₁ and the electrodepads, the manufacturing steps would not be complex, which would notincrease the manufacturing cost and also the properties of the productchip PC would not deteriorate. For example, as illustrated in FIG. 5, ifthe TEG element T₁ is not provided in the product chip PC, theflattability characteristics of the insulating layers 5 and 6deteriorate due to the CMP process, the etching process and the like, sothat the properties of the product chip PC would deteriorate.

In FIG. 6, which illustrates a second embodiment of the semiconductordevice (wafer) according to the present invention, a semiconductor waferis divided into a plurality of product chips PC with no test chip. Eachof the product chips PC is the same as those of FIG. 1.

In FIG. 7, which illustrates a third embodiment of the semiconductordevice (wafer) according to the present invention, a semiconductor waferis divided into a plurality of test chips TC with no product chip. Eachof the test chips TC is the same as those of FIG. 1.

Note that, in an actual wafer manufacturing process, one or more lotseach formed by a plurality of semiconductor wafers are processed by abatch process. Therefore, if each lot is formed by a plurality ofsemiconductor wafers as illustrated in FIG. 6 and one semiconductorwafer as illustrated in FIG. 7, the properties of the product chips PCof the semiconductor wafers as illustrated in FIG. 6 would notdeteriorate due to the absence of test chips TC, while the properties ofthe product chips PC of the semiconductor wafers of FIG. 6 can beevaluated by testing the test chips TC of the semiconductor wafer ofFIG. 7.

In the above-described embodiments, although the through structures 5 aand the connection layers 5 b are not provided for the TEG element T₁ ofthe product chip PC, the through structures 5 a and the connectionlayers 5 b can be provided for the TEG element T₁ of the product chip PCas illustrated in FIG. 8, thus further improving the flattabilitycharacteristics of the semiconductor wafer.

In the above-described embodiments, although the TEG elements T₁ and T₂are formed completely beneath the electrode pads P₃ and P₆,respectively, the TEG elements T₁ and T₂ can be formed partly beneaththe electrode pads P₃ and P₆, respectively, as illustrated in FIG. 9.Even in this case, a third party including users can hardly find the TEGelements T₁ and T₂ due to the presence of the insulating layers 5 and 6.Also, if there is a space around the electrode pads, the TEG elements T₁and T₂ can be provided in the periphery of the electrode pads T₃ and T₆as illustrated in FIG. 10. Even in this case, a third party includingusers can hardly find the TEG elements T₁ and T₂ due to the presence ofthe insulating layers 5 and 6.

In the above-described embodiments, although only one TEG element isprovided in each of the chips, a plurality of TEG elements each for oneof the electrode pads can be provided as illustrated in FIG. 11. Notethat the connection lines for the TEG elements T₅, T₇ and T₈ are omittedto simplify the description. In this case, the size of the source/drainregions, the gate width and the gate length of one TEG element aredifferent from those of the other TEG elements, thus carrying outvarious kinds of test operations. Also, as illustrated in FIG. 12, ifthere is a large-sized electrode pad such as P₄ or P₅ where a pluralityof TEG elements can be formed, a plurality of TEG elements such as T₁,T₂ and T₃ and T₄, T₅ and T₆ are formed beneath the electrode pads P₄ andP₅. Note that, in the TEG elements T₄, T₅ and T₆ of FIG. 12, the gatesare connected by a connection line C₈ to the electrode pad P₈, and thesources are connected by a connection line C₇ to the electrode pad P₇.Also, in the TEG element T₆, the drain is connected via connection lineC₆ to the electrode P₆. The drains of the TEG elements T₄ and T₅ areconnected by connection lines to the other electrode pads; however, suchconnection lines are omitted to simplify the description. Even in thiscase, the size of the source/drain regions, the gate width and the gatelength of one TEG element are different from those of the other TEGelements, thus carrying out various kinds of test operations.

Further, when the fine structure of elements has been developed whilethe accuracy of manufacturing equipment such as bonding equipment hasbeen not so improved, electrode pads may be much larger than circuitelements including TEG elements as shown in FIG. 13, where the electrodepads P₄ and P₅ of FIG. 12 are much larger. In this case, circuitelements CE₁, CE₂ and CE₃ as well as the TEG elements T₁, T₂ and T₃ areprovided beneath the electrode pad P₄ and circuit elements CE₄, CE₅ andCE₆ are provided beneath the electrode pad P₅.

Additionally, in the above-described embodiments, the TEG elements canbe formed of other active elements such as bipolar transistors, orpassive elements such as resistance elements or capacitance elements.For example, as illustrated in FIGS. 14A and 14B, the TEG elements T₁and T₂ are constructed by resistance elements formed by the connectionlayers 4 b. On the other hand, as illustrated in FIGS. 15A and 15B, theTEG elements T₁ and T₂ are constructed by capacitance elements formed bythe layers 2 and 4 b and the insulating layers 4 therebetween.

1. A semiconductor device, comprising: a semiconductor substrate; an electrode pad of a plurality of electrode pads formed over said semiconductor substrate; at least one test element formed in a region of said semiconductor substrate beneath said electrode pad, said test element being electrically isolated from any of the electrode pads that are disposed outside of said region, and from said electrode pad; and at least another test element formed beneath another electrode pad of the plurality of electrode pads in said semiconductor substrate, wherein said another electrode pad is electrically isolated from any element in said semiconductor device.
 2. The semiconductor device as set forth in claim 1, wherein said semiconductor device further comprises at least one circuit element formed in said region, and wherein said at least one circuit element is electrically connected to a group of said electrode pads disposed outside of said region, and to said electrode pad.
 3. The semiconductor device as set forth in claim 1, wherein said test element is arranged completely beneath said electrode pad.
 4. The semiconductor device as set forth in claim 1, wherein said test element is arranged partly beneath said electrode pad.
 5. The semiconductor device as set forth in claim 1, wherein said test element is arranged in a periphery of said electrode pad.
 6. The semiconductor device as set forth in claim 1, wherein said test element comprises one of a transistor element, a resistance element and a capacitance element.
 7. A semiconductor device, comprising: a semiconductor substrate; an electrode pad of a plurality of electrode pads formed over said semiconductor substrate; at least one test element formed in a region of said semiconductor substrate beneath said electrode pad; at least one circuit element formed in said region, and at least another test element formed beneath another electrode pad of the electrode pads in said semiconductor substrate, wherein said at least one test element is electrically isolated from any of the electrode pads that are disposed outside of said region, and from said electrode pad, wherein said at least one circuit element is electrically connected to a group of said electrode pads that is disposed outside of said region, and wherein said another electrode pad is electrically isolated from any element in said semiconductor device.
 8. The semiconductor device as set forth in claim 1, wherein a group of said plurality of electrode pads is electrically connected to said at least one circuit element via a plurality of connection lines.
 9. The semiconductor device as set forth in claim 1, wherein an area between said electrode pad and said test element comprises a plurality of insulating layers rather than a through structure.
 10. The semiconductor device as set forth in claim 7, wherein said group of said plurality of electrode pads is electrically connected to said at least one circuit element via a plurality of connection lines. 